_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. MAX4888B/max4888c up to 8.0gbps dual passive switches 19-5706; rev 0; 12/10 typical operating circuit general description the MAX4888B/max4888c dual double-pole/double- throw (2 x dpdt), high-speed passive switches are ideal for switching two half-lanes of pci express m (pcie) data between two possible destinations. these devices feature a dual digital control input to switch signal paths. the max4888c is intended for use in systems where both the input and output are capacitively coupled (e.g., sas, sata, xaui, and pcie) and provides a 10 f a (typ) source current and a 60k i (typ) internal biasing resistor to gnd at the aout_ and bout_ pins. the devices are fully specified to operate from a single +3.3v (typ) power supply. both devices are available in an industry-standard 3.5mm x 5.5mm, 28-pin tqfn package. they operate over the -40 n c to +85 n c extend - ed temperature range. applications desktop pcs notebook pcs servers features s single +3.3v power-supply voltage s supports pcie gen i, gen ii, and gen iii data rates s supports up to and including 6.0gbps sas/sata signals s supports other high-speed interfaces (e.g., xaui) s superior bandwidth return loss s small, 3.5mm x 5.5mm, 28-pin tqfn package ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. pci express is a registered trademark of pci-sig corp. evaluation kit available max4888c v cc gnd connection select aouta+ max4888c v cc gnd aouta- bouta+ sel selb sel selb pcie host bouta- ain+ ain- bin+ bin- ain+ ain- bin+ bin- aoutb+ aoutb- boutb+ sas host note: ca pacitive coupling w as omitted to simplify illustra tion. pcie device sas device boutb- aouta+ aouta- bouta+ bouta- aoutb+ aoutb- boutb+ boutb- part temp range pin-package MAX4888B eti+ -40 n c to +85 n c 28 tqfn-ep* max4888c eti+ -40 n c to +85 n c 28 tqfn-ep*
MAX4888B/max4888c up to 8.0gbps dual passive switches 2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd, unless otherwise noted.) v cc .......................................................................... -0.3v to +4v sel, selb, ain+, ain-, bin+, bin-, aouta+, aouta-, aoutb+, aoutb-, bouta+, bouta-, boutb+, boutb- (note 1) .. -0.3v to (v cc + 0.3v) continuous current (ain_ to aouta_/aoutb_, bin_ to bouta_/boutb_) .......................................... q 15ma peak current (ain_ to aouta_/aoutb_, bin_ to bouta_/boutb_) (pulsed at 1ms, 10% duty cycle) ................................ q 70ma continuous current (sel, selb) .................................... q 10ma peak current (sel, selb) (pulsed at 1ms, 10% duty cycle) ................................ q 10ma continuous power dissipation (t a = +70 n c) tqfn (derate 28.6mw/ n c above +70 n c) .................. 2286mw operating temperature range .......................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v cc = 3.3v q 10%, t a = -40 n c to +85 n c , unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 n c, unless otherwise noted.) (note 3) absolute maximum ratings note 1: signals on sel, selb, ain_, bin _, aouta_, aoutb_, bouta_, and boutb_ exceeding v cc or gnd are clamped by internal diodes. limit forward-diode current to maximum current rating. package thermal characteristics (note 2) note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . tqfn junction-to-ambient thermal resistance ( q ja ) .......... 35 c/w junction-to-case thermal resistance ( q jc ) ................. 2 c/w parameter symbol conditions min typ max units dc performance analog-signal range v input ain_, bin_, aouta_, bouta_, aoutb_, boutb_ -0.3 v cc - 1.8 v on-resistance r on v cc = +3.0v, i ain_ = i bin_ = 15ma, v_ outa_ = v_ outb_ = 0v, 1.2v 6.4 8.4 i on-resistance match between channels d r on v cc = +3.0v, i ain_ = i bin_ = 15ma, v_ outa_ = v_ outb_ = 0v (note 4) 0.2 1.5 i on-resistance flatness r flat(on) v cc = +3.0v, i ain_ = i bin_ = 15ma, v_ outa_ = v_ outb_ = 0v, 1.2v (note 5) 0.3 1 i _outa_ or _outb_ off-leakage current i_ outa_(off), i_ outb_(off) v cc = +3.6v, v ain_ = v bin_ = 0v, 1.2v; v _outa_ or v _outb_ = 1.2v, 0v (MAX4888B) -1 +1 f a ain_, bin_ on-leakage current i ain_(on), i bin_(on) v cc = +3.6v , v ain_ = v bin_ = 0v, 1.2v; v _outa_ or v _outb_ = v ain_ = v bin_ or unconnected (MAX4888B) -1 +1 f a output short-circuit current all other ports are unconnected (max4888c) 5 15 f a output open-circuit voltage all other ports are unconnected (max4888c) 0.2 0.6 0.9 v
MAX4888B/max4888c up to 8.0gbps dual passive switches 3 electrical characteristics (continued) (v cc = 3.3v q 10%, t a = -40 n c to +85 n c , unless otherwise noted. typical values are at v cc = 3.3v, t a = +25 n c, unless otherwise noted.) (note 3) note 3: all units are 100% production tested at t a = +85 n c. limits over the operating temperature range are guaranteed by design and characterization and are not production tested. note 4: d r on = r on(max) - r on(min) . note 5: flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog-signal range. note 6: guaranteed by design; not production tested. parameter symbol conditions min typ max units ac performance switch turn-on time t on_sel z s = z l = 50 i 65 ns switch turn-off time t off_sel z s = z l = 50 i , figure 1, measured at 500mhz 7 ns propagation delay t pd z s = z l = 50 i , figure 2, measured at 500mhz 43 ps output skew between pairs t sk1 z s = z l = 50 i , figure 2, measured at 500mhz 8 ps output skew between same pair t sk2 z s = z l = 50 i , figure2 10 ps differential return loss (note 6) s dd11 0hz < f p 2.8ghz -14 db 2.8ghz < f p 5.0ghz -8 5.0ghz < f p 8.0ghz -5 f > 8.0ghz -1 differential insertion loss s dd21 table 1 db bandwidth s dd12 /s dd21 8 ghz differential crosstalk (note 6) s ddctk 0hz < f p 2.5ghz -30 db 2.5ghz < f p 5.0ghz -25 5.0ghz < f p 8.0ghz -35 f > 8.0ghz -35 differential off-isolation (note 6) s dd21_off 0hz < f p 2.5ghz -15 db 2.5ghz < f p 5.0ghz -12 5.0ghz < f p 8.0ghz -12 f > 8.0ghz -12 control input input logic-high v ih 1.4 v input logic-low v il 0.6 v input logic hysteresis v hyst 130 mv power supply power-supply range v cc 3.0 3.6 v v cc supply current i cc 1 ma
MAX4888B/max4888c up to 8.0gbps dual passive switches 4 test circuits/timing diagrams figure 1. switching time table 1. insertion loss mask load source v out z l sel z s 10% 90% 50% 50% t on_sel t off_sel v out sel the frequency of the signal should be above the highpass filter corner of the coupling capacitors. MAX4888B max4888c frequency range (ghz) maximum insertion loss (db) 0 to 2.5 1/3 x f ghz + 17/30 2.5 to 5 2/5 x f ghz - 2/5 5 to 8 18/5 x f ghz - 4/15 greater than 8 2 x f ghz - 12
MAX4888B/max4888c up to 8.0gbps dual passive switches 5 test circuits/timing diagrams (continued) figure 2. propagation delay and output skew load source v outp z l v outn z l sel calibration traces v s+ z s v s- z s v calp z l v caln z l v sc+ z s v sc- z s 50% 50% vcm 50% 50% vcm vcm vcm t pdr t pdf t sk1 t sk2 v outn after eliminating source and cable skews. v outp t pd = max (t pdr , t pdf ) t skew = max (t sk1 , t sk2 ) v outp - v outn v calp - v caln MAX4888B max4888c
MAX4888B/max4888c up to 8.0gbps dual passive switches 6 typical operating characteristics (v cc = 3.3v, t a = +25 n c, unless otherwise noted.) differential crosstalk vs. frequency MAX4888B/c toc09 frequency (ghz) differential crosstalk (db) 8 6 2 4 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 10 differential off-isolation vs. frequency MAX4888B/c toc08 frequency (ghz) differential off-isolation (db) 8 2 6 4 -70 -60 -50 -40 -30 -20 -10 0 -80 0 10 differential insertion loss vs. frequency MAX4888B/c toc07 frequency (ghz) differential insertion loss (db) 8 6 2 4 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 -20 0 10 MAX4888B max4888c mask differential return loss vs. frequency MAX4888B/c toc06 frequency (ghz) differential return loss (db) 8 2 6 4 -70 -60 -50 -40 -30 -20 -10 0 -80 0 10 MAX4888B max4888c mask turn-on/off time vs. supply voltage MAX4888B/c toc05 v cc (v) turn-on/off time (ns) 3.5 3.4 3.3 3.2 3.1 10 20 30 40 50 60 70 80 90 100 0 3.0 3.6 t on_sel t off_sel logic threshold vs. supply voltage MAX4888B/c toc04 v cc (v) logic threshold (v) 3.5 3.4 3.3 3.2 3.1 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.8 3.0 3.6 v ih v il supply current vs. temperature MAX4888B/c toc03 temperature (c) supply current (a) 60 35 10 -15 150 200 250 300 350 100 -40 85 MAX4888B max4888c v cc = 3.6v v cc = 3.3v v cc = 3.0v v cc = 3.6v v cc = 3.3v v cc = 3.0v on-resistance vs. v _in_ MAX4888B/c toc02 v _in_ (v) r on ( ) 1.2 0.9 0.3 0.6 3 4 5 6 8 7 9 10 2 0 1.5 t a = +85c t a = +25 c t a = -40c on-resistance vs. v _in_ MAX4888B/c toc01 v _in_ (v) r on ( ) 1.5 1.2 0.3 0.6 0.9 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 4.0 0 1.8 v cc = 3.0v v cc = 3.3v v cc = 3.6v
MAX4888B/max4888c up to 8.0gbps dual passive switches 7 pin configuration pin description top view tqfn 11 12 13 14 gnd v cc gnd v cc 28 + 27 26 25 gnd v cc gnd v cc 1 2 3 4 5 6 7 8 9 1 0 24 23 22 21 20 19 18 17 16 15 gnd boutb- boutb+ bin- bin+ aoutb- aoutb+ ain- ain+ gnd selb gnd bouta- bouta+ v cc gnd aouta- aouta+ gnd sel *ep *connect exposed pad to gnd. MAX4888B max4888c pin name function 1, 10, 11, 13, 16, 20, 23, 26, 28 gnd ground 2 ain+ analog switch 1, common positive terminal 3 ain- analog switch 1, common negative terminal 4 aoutb+ analog switch 1, normally open positive terminal 5 aoutb- analog switch 1, normally open negative terminal 6 bin+ analog switch 2, common positive terminal 7 bin- analog switch 2, common negative terminal 8 boutb+ analog switch 2, normally open positive terminal 9 boutb- analog switch 2, normally open negative terminal 12, 14, 19, 25, 27 v cc positive supply-voltage input. connect v cc to a 3.0v to 3.6v supply voltage. bypass v cc to gnd with a 0.1 f f ceramic capacitor placed as close as possible to the device. see the board layout section. 15 selb control signal input. selb has a 70k i (typ) pullup resistor to v cc . if selb is not in use, leave unconnected. 17 bouta- analog switch 2, normally closed negative terminal 18 bouta+ analog switch 2, normally closed positive terminal 21 aouta- analog switch 1, normally closed negative terminal 22 aouta+ analog switch 1, normally closed positive terminal 24 sel control signal input. sel has a 70k i (typ) pulldown resistor to gnd. ep exposed pad. connect ep to gnd.
MAX4888B/max4888c up to 8.0gbps dual passive switches 8 functional diagram/truth table max4888c aouta+ ain+ aouta- ain- aoutb+ aoutb- bouta+ bin+ bouta- bin- selb v cc v cc boutb+ boutb- gnd sel control MAX4888B aouta+ ain+ aouta- ain- aoutb+ aoutb- bouta+ bin+ bouta- bin- selb v cc v cc boutb+ boutb- gnd sel control 0 (default) 1 0 (default) 1 sel 0 0 1 (default) 1 (default) selb off off on off ain_, bin_ to aout a_, bout a_ on on off on ain_, bin_ to aoutb_, boutb_
MAX4888B/max4888c up to 8.0gbps dual passive switches 9 detailed description the MAX4888B high-speed passive switch routes high- speed differential signals such as pcie, sas, sata, and xaui from one source to two possible destina - tions or vice versa. the MAX4888B is ideal for routing pcie signals to change the system configuration. the max4888c features a 10 f a (typ) source current and a 60k i (typ) internal biasing resistor to gnd at the aouta_, bouta_, aoutb_, and boutb_ terminals. the max4888c is ideal for circuits that are capacitively coupled at both the output and input. these devices are protocol independent and can be used to switch two dif - ferent protocol signals over the same physical lane. they feature dual digital control inputs (sel, selb) to switch signal paths. sel has a 70k i (typ) pulldown resistor to gnd and selb has a 70k i (typ) pullup resistor to v cc . these devices are fully specified to operate from a single 3.0v to 3.6v power supply. digital control input (sel, selb) the devices provide dual digital control inputs (sel, selb) to select the signal path between the ain_, bin_ and aouta_, bouta_ or aoutb_, boutb_ chan - nels. in most cases sel is chosen and selb is uncon - nected. the truth table for the devices is depicted in the functional diagram/truth table . sel has a 70k i (typ) pulldown resistor to gnd and selb has a 70k i (typ) pullup resistor to v cc . analog-signal levels the devices accept signals from -0.3v to (v cc - 1.8v). signals on the ain+ and bin+ channels are routed to either the aouta+, bouta+ or aoutb+, boutb+ channels. signals on the ain- and bin- channels are rout - ed to either the aouta-, bouta- or aoutb-, boutb- channels. the devices are bidirectional switches, allow - ing ain_, bin_ and aouta_, bouta_, aoutb_, and boutb_ to be used as either inputs or outputs. applications information high-speed switching the devices primary applications are aimed at sharing resources. for example, a single lane of pcie or sas can be shared between a single host and two devices. this could be used for redundancy or to share resources such as a physical lane or route a lane between one host and two devices or two hosts and one device. board layout high-speed switches require proper layout and design procedures for optimum performance. keep controlled impedance pcb traces as short as possible or follow impedance layouts per the pcie specification. ensure that power-supply bypass capacitors are placed as close as possible to the device. multiple bypass capaci - tors are recommended. connect all grounds and the exposed pad to a large ground plane. chip information process: cmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 tqfn-ep t283555+1 21-0184 90-0123
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. MAX4888B/max4888c up to 8.0gbps dual passive switches revision history revision number revision date description pages changed 0 12/10 initial release
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